S1C17803 seiko epson corporation cmos 16-bit application specific controller 16-bit risc cpu core s1c17 (max. 33 mhz operation) 128k-byte flash rom 16k-byte ram (ivram are shared by cpu and lcdc) dsp function (multiply, multiply and accumulation, division) 10-bit adc i 2 s audio dac interface infrared remote control circuit multi dma circuit (for standard dma and lcd driver dma) usi (universal serial interface) (uart/spi/i 2 c) built-in stn lcd controller support qvga (320 240) in 1 bpp mode using ivram support qvga (320 240) in 4 bpp mode or vga (640 x 480) in 1bpp mode using external vram nand flash card interface 5v single power operation can be rea lized by 3v to 5v regulator. descriptions many kinds of machine like white goods (eg. washing machine, rice cooker , and coffee maker) can be improved user interface using display, musi c, voice, touch panel and etc. it can be operated by 5v single power suppl y using built-in 5v to 3v regulator. it is separated three groups io, each group can be set arbitrar ily voltage by multi voltage io (mvio).it can be realized the system which mixed 3v and 5v devic es easier without level shifter. internal lcdc supports qvga panel (black and white) without external memory, and it supports to display vga stn lcd panel (black and white ) or qvga stn lcd panel (16-gray scale) with external sram . it also supports an lcd driver dma function to interface with an epson s1d15xxx built-in ram lcd driver and a driver with an spi. therefore, it can connect wi th many kind of lcd driver. dsp function has 1616bits mul (multiply) instruction, 1616 32bits mac (multiply and accumulation) instruction, and 1616bits div (division) instruction. as a result, load of cpu in the voice r eproduction processing etc. is reduced. rtc and bbram can operated in an independent power supply. great energy-saving can be attempted by st opping the power supply to other circuits. lineup flash rom ram pkg 1 128k bytes 16k bytes (shared with vram) tqfp14-100pin (0.4mm pitch) 2 128k bytes 16k bytes (shared with vram) tqfp15-128pin (0.4mm pitch) 3 128k bytes 16k bytes (shared with vram) qfp5-128pin (0.5mm pitch) features technology 0.35 m al-4-layers mixed analog low power cmos process technology cpu seiko epson original 16-bit risc processor s1c17 core internal 3-stage pipeline instruction set - 16-bit fixed length - 111 basic instructions (184 including variations)
S1C17803 2 epson - compact and fast instruction set optimized for development in c language registers - eight 24-bit general-purpose registers - three special registers (24-bit 2, 8-bit 1) memory space - up to 16m bytes accessible (24-bit address) dsp mul (multiply) 16 16bits (1 cycle) mac (multiply and accumulation) 16 16 32bits (1 cycle) div (division) 16 16bits (17 to 20 cycles) internal memories flash eeprom 128k bytes ram 16k bytes (shared with vram) bbram 16 bytes (for battery backup) operating clock main clock - 1 to 33 mhz (can be divided by 1 to 32) or 32.768 khz - on-chip oscillator (crystal or ce ramic) or external clock input sub clock - 32.768 khz (typ.) for the rtc - on-chip oscillator (crystal) interrupt controller four non-maskable interrupts - reset (#reset pin or watchdog timer) - address misaligned - debug - nmi (#nmi pin or watchdog timer) 18 maskable interrupts tbd - port inputs (two systems) - dma (one system) - 16bits timer (one system) - 8bits timer (one system) - usi (one system) - adc (one system) - pwm (one system) - i 2 s (one system) - lcdc (one system) - 16-bit timers of clock generator (one system) - 8-bit timers of clock generator (one systems) - uart (one system) - i 2 c master (one system) - i 2 c slave (one system) - rtc (one system) - remc (one system) - the interrupt level (priority) of each maskable in terrupt system is configurable (levels 0 to 7).
S1C17803 epson 3 sram controller provides a 23-bit external address bus, an 8- or 16-bit width selectable data bus, and four chip enable signals to support a maximum of 16m-byte external memory space. provides an sram uma feature to access an external vram for supporting up to 16-grayscale qvga lcd panel. psc (prescaler) generates the source clo cks for the clock generator. clg (clock generator) 1 channel of 8-bit timer and 2 channels of 16-bit timer are available these timers are for uart, spi, i 2 c and multi sio. each timer can generate an underflow interrupt. pwm control capture 16-bit timer/counter 2 channels of 16-bit timer/counter with pwm output function is available. each timer can generate 2 compare-match interrupts. 3 type bit division function is available (10bits + 6bits, 9bits + 7bits, 8bits + 8bits) pwm function for sound supports 8bits and 16bits pcm data. can output monaural sound without external dac t8 (8-bit timer) 3 channels of 8-bit timer (pre-sett able down counter) are available. clock generated with the counter underflow can be output to external devices. can be used as an interval timer to trigger the adc and the usi. each timer can generate an underflow interrupt. t16a (16-bit timer) 1 channels of advanced 16-bit timer (pre-s ettable down counter) are available. capture function is available. can use 2 compare value at the same time watchdog timer 30-bit watchdog timer to generate a reset or an nmi the watchdog timer overflow period (reset or nmi interrupt period) is programmable. the watchdog timer overflow signal can be output outside the ic. rtc contains time counters (second, minut e, and hour) and calendar counters (day, day of the week, month, and year). the power source separated with the syst em power supply (lvdd/hvdd) can be used. provides the wakeup output pin and #st by input pin to control standby mode. periodic interrupts are possible. uart 1 channels of uart is available. supports irda 1.0 interface. 2-byte receive data buffer and one-byte transmit buffer are built in to support full-duplex communication. transfer rate: 150 to 460800 bps, character length: seven or ei ght bits, parity mode: even, odd, or no parity, stop bit: one or two bits
S1C17803 4 epson parity error, framing error, and overrun error detectable each channel can generate receive buffer full, trans mit buffer empty, and receive error interrupts. spi supports both master and slave modes. one-byte receive data buffer and one-byte transmit buffer are built in. data length: eight bits fixed (msb first) data transfer timing (clock phase and polarity va riations) is selectable from among 4 types. can generate receive buffer full and tr ansmit buffer empty interrupts. i 2 c supports 1 of master and 1 of slave mode. data format: 8 bits (msb first) addressing mode: 7-bit addressing ( 10-bit addressing is not supported.) supports the noise reject func tion controlled by a register. can generate an i 2 c interrupt. usi 2 channels of multi serial interface is available for uart, spi or i 2 c. spi and i 2 c master or slave mode can be selected can generate an usi interrupt. i 2 s supports universal audio i 2 s bus interface. one i 2 s output channel in 16-bits resolution. operates as the master to gener ate the bit clock, word-selec t signal, data and master clock. can generate an i 2 s interrupt. card interface generates 8- or 16-bit na nd flash interface signals. the ecc function should be implem ented in the application program. remc (infrared remote controller) outputs a modulated carrier signal and inputs remote control pulses. embedded carrier signal generator and data length counter. can generate remc interrupts. dma 4 channels table dma reload and pause function is available. dma function for lcd driver interface is available. trigger source - usi (spi/i 2 c) data receive and transmit. - i 2 s - pwm - adc lcd controller stn lcd controller supports up to 16 gray shades using frm (frame rate modulation).
S1C17803 epson 5 1/2/4 bpp (2/4/16 grayscale) monochrome lcd interface (bpp: bit-per-pixel) 16k-byte ivram (internal vram) - can be used to display up to 320 240 lcd panels in 1 bpp mode. - the ivram arbiter is provided allowing the cpu and lcd controller to access the ivram via the sram controller. the uma feature allows use of an external sram as the vram. - expands the display size up to qvga (320 240) panels in 4 bpp (16-grayscale) mode or vga (640 x 480) panels in 1 bpp mode. supports 16-bit srams for the external vram. (8-bit srams are not supported.) - the evram arbiter is provided allowing the cpu and lcd controller to access the external vram via the sram controller. supports an lcd driver dma function - allows display data transfer to the exter nal lcd driver with no software control. supported displays - single panel - single drive passive display - monochrome/grayscale stn lcd panel with a 4/8- bit data bus width sla or mla type lcd driver - lcd panels with a 4/8-bit parallel mcu interface lcd driver (lcd segment/common driver with controller) the 80 series parallel mcu interface is supported. this interface allows writing to and reading from the external lcd driver. - lcd panels with an lcd driver that supports 8/9-bit spi supports 8-bit spi with 4 lines (sck, sda, d/#c, #cs: 8-bit data). supports 9-bit spi with 3 lines (sck , sda, #cs: 8-bit data + d/#c). - lcd panels with a built-in ram lcd driver that supports 8/9-bit spi supports 8-bit spi with 4 lines (sck, sda, d/#c, #cs: 8-bit data). supports 9-bit spi with 3 lines (sck , sda, #cs: 8-bit data + d/#c). this interface allows only writing to the external lcd driver (it does not support reading from the lcd driver). supported drivers - epson s1d15xxx built-in ram lcd drivers - stn lcd drivers with a 4/8-bit parallel mcu interface (lcd segment/common driver with controller) the 80 series parallel mcu interface is supported. this interface allows writing to and reading from the external lcd driver. - stn lcd drivers that support spi supports 8-bit spi with 4 lines (sck, sda, d/#c, #cs: 8-bit data). supports 9-bit spi with 3 lines (sck , sda, #cs: 8-bit data + d/#c). this interface allows only writi ng to the external lcd driver (it does not support reading from the lcd driver). adc 10-bit a/d converter with up to 4 analog input ports can generates an end of conversion inte rrupt and an out of range interrupt. gpio (general-purpose i/o ports) maximum 93 i/o ports and 4 input ports are available. (tbd)
S1C17803 6 epson can generate input interrupts from the 29 ports selected with so ftware.(p2x, p4x, p8x, pax) *the gpio ports are shared with other peripheral function pins (uart, pwm et c.). therefore, the number of gpio ports depends on the peripher al functions used. regulator 5v to 3v conversion 5v single power supply operation multi i/o voltage the each io group of three (io1, io2, bu s) can be selected interface voltage. operating voltage iovdd1: 2.70 5.50v iovdd2: 2.70 5.50v busvdd: 2.70 5.50v lvdd: 2.70 3.60v rtcvdd: 2.70 3.60v avdd(i/o): 2.70 5.50v rgvdd: 4.50 5.50v operating temperatures -40 to 70c (flash memory erase/write) -40 to 85c (excludi ng the above-mentioned) power consumption battery backup (for memory): 0.085 a battery backup (for clock, memory): 3.7a sleep mode: 6 a halt mode (33mhz): 11 ma operating (33 mhz): 32 ma * by controlling the clocks through the clock-gear (cmu), power consum ption can be reduced. *these figures are for reference only, based on 3.3v usage without a regulator. actual figures will depend on circuit operation and core cpu processing. shipping form package: tqfp14-100pin (12 mm 12 mm 1.2 mm, 0.4 mm pin pitch) package: tqfp15-128pin (14 mm 14 mm 1.2 mm, 0.4 mm pin pitch) package: qfp5-128pin (14 mm 20 mm 3.5 mm, 0.5 mm pin pitch)
S1C17803 epson 7 block diagram user bus0 flash 128kb dma registers lcdc registers i 2 s out (1ch) t16a (1ch) c17 soc macro s1c17 cpu core peri bus clock generator (1-ch. 16-bit timer, 1-ch. 8-bit timer) uart with irda i2 c maste r i 2 c s l a v er psc 22ch. itc user bus1 lcdc mini dma (4ch) ivram interface sramc sapb bridge flashc ivram ( 16kb) dsp (mul, mac, div) remc flashc registers sramc registers wdt cmu pwm (2ch) adc (4ch) gpio & port mux t8f (3ch) usi (2ch) psc card rtc / bbram 16b bus matrix
S1C17803 8 epson semiconductor operations division seiko epson corporation ic sales department ic international sales group 421-8 hino, hino-shi, tokyo 191-8501, japan phone: +81-42-587-5814 fax: +81-42-587-5117 notice: no part of this material may be reproduced or duplicated in any fo rm or by any means without the written permission of seiko eps on. seiko epson reserves the right to make c hanges to this material without notice. se iko epson does not assume any liability of a ny kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit and, furt her, there is no representation that this material is app licable to products requiring high level reliab ility, such as, medical products. moreo ver, no license to any intellectual property rights is granted by implication or otherwise, and there is no representation or warranty that any thing made in accordance with this material will be free from any patent or copy right infringement of a third party. this material or portio ns thereof may contain technology or the subject relati ng to strategic products under the control of the foreign exchange and foreign trade la w of japan and may require an export license from the ministry of economy, trade and industry or other approval from another government ag ency. ?seiko epson corporation 2009, all rights reserved. http://www.epson.jp/device/semicon_e/ ? epson electronic devices website document code: 411708100 first issue mar, 2009
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